Remove outdated images and metadata from notes; add new styles and plugin configuration

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---
title: Algorithms & Data Structures
description:
date: 2025-02-17T08:52:10+00:00
draft: false
tags:
- c

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---
title: Binary Operations
description:
date: 2025-02-17T08:37:24+00:00
draft: false
tags:
- computer-science
@@ -122,21 +121,21 @@ Add 2, single-digit binary numbers.
| 1 | 0 | 0 | 1 |
| 1 | 1 | 1 | 0 |
![[image68.png]]
![image68](image68.png)
#### Full Adder
When adding 2 binary numbers, one operation might return a carry value, which the `half adder` can't accept, as it only has 2 inputs.
![[image69.png]]
![image69](image69.png)
To solve this issue, a `full adder` accepts 3 inputs.
![[image70.png]]
![image70](image70.png)
#### 8-Bit Adder
![[image71.png]]
![image71](image71.png)
### Subtraction
@@ -153,7 +152,7 @@ Subtract 2, single-digit binary numbers.
| 1 | 0 | 1 | 0 |
| 1 | 1 | 0 | 0 |
![[image72.png]]
![image72](image72.png)
#### Full Subtractor
@@ -170,11 +169,11 @@ A `full subtractor` accepts the borrow value, allowing us to chain results.
| 1 | 1 | 0 | 0 | 0 |
| 1 | 1 | 1 | 1 | 1 |
![[image73.png]]
![image73](image73.png)
#### 8-Bit Subtractor
![[image74.png]]
![image74](image74.png)
### Multiplication
@@ -198,7 +197,7 @@ First, multiply the top number to every digit of the bottom one, and then add th
#### 2-Bit By 2-Bit Multiplier
![[image75.png]]
![image75](image75.png)
### Division

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---
title: C Language
description:
date: 2025-02-17T08:54:40+00:00
draft: false
tags:
- c

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---
title: C Snippets
description:
date: 2025-02-17T08:56:33+00:00
draft: false
tags:
- c

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---
title: Compiling [MAKE / GCC]
description:
date: 2025-02-17T08:59:53+00:00
draft: false
tags:
- c

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---
title: CPU Architecture
description:
date: 2025-02-17T08:06:50+00:00
draft: false
tags:
- computer-science
@@ -14,33 +13,33 @@ showToc: true
### Registers
We can combine registers to reduce the amount of wires needed.
![[image8.png]]
![image8](image8.png)
Using a data bus (wiring at the top) and a binary decoder, we can select which register to read/write to.
### Memory
![[image9.png]]
![image9](image9.png)
## Assembly
Assembly is a human-friendly representation of code: binary values that a computer can understand.
![[image10.png]]
![image10](image10.png)
An assembler converts ASM instructions into machine code, which is given to the CPU as input.
### Arithmetic Operations
For example, a simple computer architecture could use `00` to represent arithmetic operations.
![[image11.png]]
![image11](image11.png)
To decide which type of operation to execute (subtraction, multiplication, addition, etc), the 3rd and 4th bits could be used.
![[image12.png]]
Using a [[ready/binary-operations/index]], we can build an inefficient, but simple circuit to do this.
![[image13.png]]
![image12](image12.png)
Using a [index](ready/binary_operations/index.md), we can build an inefficient, but simple circuit to do this.
![image13](image13.png)
This type of circuit is an Arithmetic Logic Unit (ALU).
### Memory Operations
Of course, assembly can also provide instructions to store or load values.
![[image14.png]]
![image14](image14.png)
#### Load
@@ -48,7 +47,7 @@ Of course, assembly can also provide instructions to store or load values.
LOAD R2 1000 ;Load into register 2 the value in the memory address 1000
```
![[image15.png]]
![image15](image15.png)
#### Store
@@ -56,68 +55,68 @@ LOAD R2 1000 ;Load into register 2 the value in the memory address 1000
STORE R1 0110 ;Store the value in register 1 into the 0110 memory address
```
![[image16.png]]
![image16](image16.png)
#### Select Which Instruction to Execute (first 2 bits)
To decide which operation to execute, a binary decoder can be used.
![[image17.png]]
![image17](image17.png)
For memory operations, the 3rd and 4th bits are used to select which register to use.
![[image18.png]]
![image18](image18.png)
The last 4 bits represent the memory address to read/write to.
![[image19.png]]
![image19](image19.png)
### Instruction Register
For the instruction to be given, it is stored in a special register: An Instruction Register.
![[image20.png]]
![image20](image20.png)
### Optimization
We can use a single Binary Decoder instead of two, to achieve the same result. (Optimization on the right pane)
![[image21.png]]
![image21](image21.png)
Different architectures can have the exact same functionality, while being implemented differently, or even having different instructions. This is why code that is compiled for Intel x64 is not compatible with ARM or RISC-V.
## Control Unit
We can finally add the ALU (Arithmetic Logic Unit) we built before into the new circuit, like so:
![[image22.png]]
![image22](image22.png)
The gray trapezoids are multiplexers:
![[image23.png]]
![image23](image23.png)
The output value is then stored in a temporary register, before replacing the first operand register's value.
The component we just built to control the `ALU` is part of a `Control Unit`. The full `control unit` is very complex, as it needs to handle every possible instruction. (So far, we have seen how to implement the `ALU` and `RAM`.)
![[image24.png]]
![image24](image24.png)
Each register in the `CU` has a specific purpose, unlike `RAM`, which can be used to store any values.
![[image25.png]]
![image25](image25.png)
To read the first instruction, the `CU` will **fetch** data from the first address in memory.
![[image26.png]]
![image26](image26.png)
After **fetching**, the `CU` will **decode** the instruction: interpret the bit sequence in the `instruction register`, to send the necessary signals to the components that will **execute** the instruction. We can finally load instructions into the instruction register.
![[image27.png]]
![image27](image27.png)
Then, the `CU` increments 1 byte, to point the `address register` to the next instruction. (Modern architectures increment different values, as the instruction set is more complex)
If the instruction is an arithmetic operation, the steps are similar. The ALU stores the output in a temporary register, which overwrites the register 0 with the result. The result can then be stored in `RAM`.
![[image28.png]]
![image28](image28.png)
## Load a Program Into Memory
So far, we can store instructions in memory, but it is also necessary to store values, besides from the instructions themselves.
For example:
![[image29.png]]
![image29](image29.png)
This program uses 2 numeric values. The first 2 instructions load these values into the registers, and then, these values are added together and stored in another memory address. The final instruction, `HALT`, marks the end of the program, to make sure the `CU` does not attempt to read the number 20 as an instruction.
If the program is extended, all memory addresses must be altered. To fix this issue, we can instead store values at the end of the memory stack.
![[image30.png]]
![image30](image30.png)
## Conditions and Loops
To create a loop, we can simply jump to a smaller address in memory.
![[image31.png]]
![image31](image31.png)
Internally, the `JMP` command overwrites the Address Register, making it so that the next CPU **cycle** *fetches* the chosen memory address, instead of the next one.
![[image32.png]]
![image32](image32.png)
### Flags
Sometimes, we might want to loop only if a certain condition is met.
For context, imagine subtracting a number from itself. In this case, the ALU will provide some extra information, using 1 bit registers called `flags`.
![[image33.png]]
![image33](image33.png)
| N | Flag | Description |
| --- | ------------ | --------------------------------------------------------- |
@@ -144,19 +143,19 @@ $$a - 5 = b$$
| a < 5 | a == 5 | a > 5 |
For example:
![[image34.png]]
![image34](image34.png)
An `IF` statement works in the exact same way, but without the need to loop:
![[image35.png]]
![image35](image35.png)
Note: These instructions are not from any real architecture. These are examples for this simple, custom architecture.
## Clock
The final piece of the puzzle is the clock. A clock can give us time before a circuit loops.
![[image36.png]]
![image36](image36.png)
This is necessary, because energy travels extremely quickly, and so, all memory would be reset before we could even use the stored values. Each clock tick corresponds to an action the `CU` performs (fetch, decode and execute).
A `Data FLIP-FLOP`, for example, uses the clock to store data, acting as the manual `RESET` input.
![[image37.png]]
![image37](image37.png)
This circuit can be used to build a single bit register.
![[image38.png]]
![image38](image38.png)
To generate a clock pulse, we can use a circuit similar to this one:
![[image39.png]]
![image39](image39.png)

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---
title: Databases [SQL]
description:
date: 2025-02-17T08:27:35+00:00
draft: false
tags:
- programming
@@ -15,13 +14,13 @@ showToc: true
A "table" written into a single file. The most common file type for this purpose is `CSV`.
The `CSV` format reads each line as a row, and each comma-separated value as a column.
The first row on a `CSV` file is used to describe the data in each column. If a `,` is present on the dataset, surround that entry with `"` to 'escape' it.
These files can be read and written to using languages like [[c-language]] and [[python]].
These files can be read and written to using languages like [c-language](../c-language.md) and [python](../python.md).
## Relational Databases
Instead of using a single table, a relational database can store data in multiple tables, and then define relationships between them.
Each table must have one column with an unique key that identifies each row.
![[image94.png]]
![image94](image94.png)
### Relationships
@@ -229,7 +228,7 @@ genres.show_id WHERE id =
#### Many-to-many
![[image95.png]]
![image95](image95.png)
```SQL
-- Select every person who starred in a show

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---
title: Diodes
description:
date: 2025-02-17T08:18:09+00:00
draft: false
tags:
- electronics

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---
title: Encryption [GPG]
description:
date: 2025-02-17T09:02:06+00:00
draft: false
tags:
- networking

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---
title: Flask
description:
date: 2025-02-17T09:01:01+00:00
draft: false
tags:
- programming

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---
title: Debugging [GDB]
description:
date: 2025-02-17T08:16:48+00:00
draft: false
tags:
- programming

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---
title: Version Control [GIT]
description:
date: 2025-02-17T08:58:11+00:00
draft: false
tags:
- programming

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---
title: HTML
description:
date: 2025-02-17T09:11:23+00:00
draft: false
tags:
- web

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---
title: HTTP [CURL]
description:
date: 2025-02-17T09:22:33+00:00
draft: false
tags:
- networking

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---
title: HTTPS and SSL Certificates
description:
date: 2025-02-17T09:17:30+00:00
draft: false
tags:
- networking
@@ -17,7 +16,7 @@ The `http` protocol sends data as plaintext, which is an issue when sharing sens
## TLS
TLS is a form of [[encryption]], used to secure HTTPS connections.
TLS is a form of [encryption](encryption.md), used to secure HTTPS connections.
TLS replaces SSL (a deprecated protocol), however, the term SSL is still used often.
### Handshake

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---
title: IRC
description:
date: 2025-02-17T09:13:13+00:00
draft: false
tags:
- networking
@@ -17,7 +16,7 @@ IRC is a very simple communication protocol that allows users to chat in real ti
### Server
To be able to communicate, users must connect to a server. Each server has its own rules, bots and commands. The IRC protocol itself does not implement encryption, however, [[https-ssl-certs|SSL Certificates]] can be used to establish a secure connection **with the server**.
To be able to communicate, users must connect to a server. Each server has its own rules, bots and commands. The IRC protocol itself does not implement encryption, however, [SSL Certificates](../https-ssl-certs) can be used to establish a secure connection **with the server**.
Every message sent **can be read by the server**, including **private messages** between users.
Separate IRC instances can communicate. This concept is often called **server federation**. This allows for users in different servers to send messages to each other.
@@ -163,7 +162,7 @@ services:
```
To properly configure your server, be sure to read the [containers documentation](https://hub.docker.com/r/inspircd/inspircd-docker/).
This container generates a self-signed SSL certificate for secure connections, however, it won't be accepted by actual clients. Refer to my [[https-ssl-certs|SSL guide]] to generate a real certificate for TLS to work. After generating your certificate, simply replace the old one with it.
This container generates a self-signed SSL certificate for secure connections, however, it won't be accepted by actual clients. Refer to my [SSL Guide](../https-ssl-certs) to generate a real certificate for TLS to work. After generating your certificate, simply replace the old one with it.
### Linux
@@ -189,7 +188,7 @@ Finally, start `inspircd`.
sudo systemctl start inspircd
```
To enable TLS, refer to my [[https-ssl-certs|SSL guide]]. After generating your certificate, copy it to `inspircd`'s ssl directory.
To enable TLS, refer to my [SSL Guide](../https-ssl-certs). After generating your certificate, copy it to `inspircd`'s ssl directory.
```Shell
sudo cp /etc/letsencrypt/live/irc.example.com/fullchain.pem /etc/inspircd/ssl/cert.pem

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---
title: Logic Gates
description:
date: 2025-02-17T08:25:49+00:00
draft: false
tags:
- electronics
@@ -13,7 +12,7 @@ showToc: true
## NOT
Invert the input.
![[image42.png]]
![image42](image42.png)
### Truth Table
@@ -25,7 +24,7 @@ Invert the input.
## AND
Output `1` only when both inputs are `1`.
![[image43.png]]
![image43](image43.png)
### Truth Table
@@ -39,7 +38,7 @@ Output `1` only when both inputs are `1`.
## OR
Output `1` if at least one input is `1`.
![[image44.png]]
![image44](image44.png)
### Truth Table
@@ -53,7 +52,7 @@ Output `1` if at least one input is `1`.
## NAND
An `AND` gate followed by a `NOT` gate.
![[image45.png]]
![image45](image45.png)
### Truth Table
@@ -67,7 +66,7 @@ An `AND` gate followed by a `NOT` gate.
## NOR
An `OR` gate followed by a `NOT` gate.
![[image46.png]]
![image46](image46.png)
### Truth Table
@@ -81,8 +80,8 @@ An `OR` gate followed by a `NOT` gate.
## XOR
Either input is `1`, exclusively.
![[image47.png]]
![[image48.png]]
![image47](image47.png)
![image48](image48.png)
### Truth Table
@@ -96,7 +95,7 @@ Either input is `1`, exclusively.
## XNOR
Inverted `XOR`.
![[image49.png]]
![image49](image49.png)
### Truth Table
@@ -111,13 +110,13 @@ Inverted `XOR`.
### NOT
![[image50.png]]
![image50](image50.png)
### AND
![[image51.png]]
![[image52.png]]
![image51](image51.png)
![image52](image52.png)
### OR
![[image53.png]]
![image53](image53.png)

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---
title: Memory
description:
date: 2025-02-17T08:22:26+00:00
draft: false
tags:
- computer-science
@@ -12,21 +11,21 @@ showToc: true
## Remembering Data
An `OR` gate could be used to store a single bit.
![[image76.png]]
![image76](image76.png)
If the input `A` is changed to `1`, the `OR` gate will output `1`, and then receive it.
![[image77.png]]
![image77](image77.png)
Even after the input `A` is set to `0`, the output does not change. The `OR` gate "remembers" that, at one point in the past, the `A` input was set to `1`.
![[image78.png]]
![image78](image78.png)
The inverse can be done with an `AND` gate.
![[image79.png]]
![image79](image79.png)
To remember either a `1` or a `0`, we can do the following:
![[image80.png]]
![image80](image80.png)
### AND-OR LATCH
The input `A` sets the output to `1`, and the input `B` sets the output to `0`. This circuit is able to store a bit of information, while powered on, even after both inputs are set to `0`.
A slightly more advanced and intuitive version can be built as follows:
![[image81.png]]
![image81](image81.png)
### GATED LATCH
@@ -36,39 +35,39 @@ This is not the only way to store data using logic gates, but it is one of the s
## Registers
A single bit isn't very useful, so we can use the previous circuit to create an 8bit register.
![[image82.png]]
![image82](image82.png)
## Binary Decoder
Select which circuit to activate, depending on the task at hand.
![[image83.png]]
![image83](image83.png)
## RAM
Registers don't scale well, however, as storing a large amount of data would require millions of wires.
We can organize latches in a matrix instead of a long, horizontal line.
![[image84.png]]
![image84](image84.png)
To access a specific latch, binary decoders can be used.
![[image85.png]]
![image85](image85.png)
This way, a single, short memory address can select any latch in the matrix.
### Reading and Writing to the Matrix
We can modify the latch to reduce the amount of wires needed.
![[image86.png]]
![image86](image86.png)
This new latch uses the same wire for both input and output.
![[image87.png]]
![image87](image87.png)
This circuit would store the same value on every latch, which isn't useful. With some modifications, however, we can use the memory address to select which latch to modify.
![[image88.png]]
![[image89.png]]
![image88](image88.png)
![image89](image89.png)
### Storing Bytes Instead of Bits
![[image90.png]]
![image90](image90.png)
In this example, we can provide 1 byte of information, a `write` or `read` signal, and a memory address. Since we are storing a full byte, the same memory address applies for all 8, single bit circuits.
This configuration is more commonly known as **RAM**.
To make it easier to understand, we can abstract these concepts further.
![[image91.png]]
![image91](image91.png)
The largest the Address Bus is, the more bits can be managed. This is why a 32bit CPU can't manage more than 4 GB of RAM.
![[image92.png]]
![image92](image92.png)
This kind of RAM is Static RAM (**S**RAM), which uses many transistors, making it faster, but more expensive to produce than **D**RAM.

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---
title: Password Manager [PASS]
description:
date: 2025-02-17T09:19:30+00:00
draft: false
tags:
- tools
@@ -17,10 +16,10 @@ There are many options available, however, *pass* is one of the simplest ones.
## Pass
*Pass* uses [[encryption]] to encrypt your passwords. If you don't have one already, use GPG to generate a personal key.
*Pass* uses [encryption](encryption.md) to encrypt your passwords. If you don't have one already, use GPG to generate a personal key.
Besides from allowing you to read your passwords, *pass* can be scripted, providing your passwords to scripts and other programs securely.
Instead of a database, *pass* stores every password in separate files, inside a directory called `password-store`. You can use *pass* to organize passwords just like regular files in the filesystem.
Pass also integrates with [[git|Git]], allowing you to undo changes, rollback to a previous state, and set a remote repository to save them on.
Pass also integrates with [Git](git.md), allowing you to undo changes, rollback to a previous state, and set a remote repository to save them on.
### Initialize Pass

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---
title: Python
description:
date: 2025-02-17T09:23:25+00:00
draft: false
tags:
- python

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---
title: SSH
description:
date: 2025-02-17T09:21:16+00:00
draft: false
tags:
- networking

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---
title: Terminal Multiplexer [TMUX]
description:
date: 2025-02-17T08:34:57+00:00
draft: false
tags:
- tools
@@ -23,7 +22,7 @@ showToc: true
- **Windows** (A session contains windows. These behave like tabs in other programs.)
- **Panes** (A split in the window, each with its own terminal instance.)
![[tmux_design.png]]
![tmux_design](tmux_design.png)
## [Commands](https://tmuxcheatsheet.com/)

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---
title: Transistors
description:
date: 2025-02-17T08:14:53+00:00
draft: false
tags:
- electronics
@@ -26,25 +25,25 @@ Base --(--|<)
### Switch
If the `base` pin is provided with energy, the transistor allows current to flow in the main circuit.
![[image.png]]
![image](image.png)
### Amplifier
Altering the voltage given to the `base` pin allows us to control a larger voltage in the main circuit.
![[image1.png]]
![image1](image1.png)
## Types of Transistor
### NPN
An NPN transistor combines the `base` pin and `collector` pin.
![[image2.png]]
![image2](image2.png)
> Note: Even if the collector pin is disconnected from the circuit, a small amount of current still passes through. ![[image3.png]]
> Note: Even if the collector pin is disconnected from the circuit, a small amount of current still passes through. ![image3](image3.png)
### PNP
A PNP transistor receives energy through the `emitter` pin, and then divides it to the remaining pins.
![[image4.png]]
![image4](image4.png)

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@@ -1,7 +1,6 @@
---
title: WSL2
description:
date: 2025-02-17T09:18:31+00:00
draft: false
tags:
- tools